Computer Architecture Cheat Sheet

Computer System Components

Component	Function	Characteristics	Performance Metrics
CPU (Central Processing Unit)	Execute instructions, perform calculations	ALU, Control Unit, Registers	Clock speed, MIPS, FLOPS
Memory (RAM)	Store data and instructions temporarily	Fast access, volatile	Capacity, speed, bandwidth
Storage	Store data permanently	Non-volatile, high capacity	Capacity, access time, transfer rate
Cache Memory	Store frequently accessed data	Fast, small, expensive	Hit rate, access time
I/O Devices	Interface with external world	Various speeds and protocols	Transfer rate, response time
System Bus	Connect components	Data, address, control lines	Bandwidth, speed

Instruction Set Architecture (ISA)

Aspect	Description	Examples	Trade-offs
Instruction Types	Categories of operations	Data transfer, ALU, control, I/O	Flexibility vs. simplicity
Addressing Modes	How operands are specified	Immediate, direct, indirect, register	Flexibility vs. complexity
CISC	Complex Instruction Set Computer	Intel x86, VAX	Rich instructions vs. complex hardware
RISC	Reduced Instruction Set Computer	ARM, MIPS, PowerPC	Simple instructions vs. more instructions
Instruction Format	Structure of machine instructions	Opcode + operands	Fixed vs. variable length

Processor Architecture

Feature	Description	Advantages	Disadvantages
Single Cycle	Execute each instruction in one clock cycle	Simple control, predictable timing	Waste of resources, long cycle time
Multi-cycle	Execute instructions in multiple cycles	Better resource utilization	More complex control
Pipelined	Overlapping execution of instructions	Higher throughput	Complexity, pipeline hazards
Superscalar	Multiple execution units in parallel	Multiple instructions per cycle	High power, complexity
VLIW	Very Long Instruction Word	Explicit parallelism	Compiler complexity, code bloat
Out-of-Order Execution	Execute instructions when operands ready	Better performance	Complex hardware

Memory Hierarchy

Level	Type	Speed	Cost per Byte	Capacity	Function
Registers	SRAM	Fastest	Highest	Smallest	CPU internal storage
L1 Cache	SRAM	Very Fast	High	Small	Immediate data access
L2 Cache	SRAM	Fast	Medium	Medium	Backup to L1 cache
L3 Cache	SRAM	Medium	Low	Large	Shared cache for cores
Main Memory	DRAM	Slow	Lowest	Large	Program storage
Secondary Storage	SSD/HDD	Slowest	Lowest	Largest	Permanent storage

Cache Memory

Concept	Description	Type/Method	Trade-offs
Mapping	How memory blocks map to cache	Direct, associative, set-associative	Speed vs. hit rate vs. complexity
Write Policy	How writes are handled	Write-through, write-back	Consistency vs. speed
Replacement Policy	Which block to replace	LRU, FIFO, Random	Performance vs. implementation
Cache Miss Types	Reasons for cache misses	Compulsory, capacity, conflict	Design optimization
Cache Coherence	Keeping caches consistent	Directory-based, snooping	Performance vs. consistency

Memory Management

Technique	Description	Advantages	Disadvantages
Segmentation	Divide memory into logical segments	Natural program structure, sharing	External fragmentation
Paging	Divide memory into fixed-size pages	No external fragmentation	Internal fragmentation
Virtual Memory	Extend physical memory with disk	Larger address space	Performance overhead
Page Tables	Map virtual to physical addresses	Flexible mapping	Memory overhead
TLB	Translation Lookaside Buffer	Fast address translation	Small, expensive

Pipeline Hazards

Hazard Type	Cause	Example	Solutions
Structural	Resource conflicts	Two instructions need same ALU	More resources, stalling
Data	Data dependencies	Instruction 2 needs result of Instruction 1	Forwarding, stalling, reordering
Control	Branch instructions	Branch direction affects next instructions	Branch prediction, delay slots

Performance Metrics

Metric	Definition	Formula	Use Case
Clock Rate	Speed of processor clock	Cycles per second (Hz)	Basic performance indicator
CPI (Cycles Per Instruction)	Average cycles per instruction	Total cycles / Total instructions	Architecture comparison
MIPS (Million Instructions Per Second)	Instruction execution rate	Instructions / (time in seconds × 10⁶)	Overall performance
Throughput	Work completed per unit time	Tasks completed / time	System performance
Response Time	Time to complete task	Completion time - Start time	User experience
Speedup	Performance improvement	Old time / New time	Comparison of systems

Parallel Processing

Approach	Description	Characteristics	Best For
Instruction Level Parallelism	Execute multiple instructions simultaneously	Pipelining, superscalar, VLIW	Single thread optimization
Data Level Parallelism	Perform same operation on multiple data items	Vector processors, SIMD	Scientific computing, graphics
Thread Level Parallelism	Execute multiple threads simultaneously	Multi-core, hyper-threading	Multi-threaded applications
Task Level Parallelism	Execute independent tasks in parallel	Multi-processing, distributed systems	Independent computations

Bus Architecture

Bus Type	Function	Characteristics	Performance Factors
Data Bus	Transfer data between components	Bi-directional, width varies	Width, frequency, protocols
Address Bus	Specify memory addresses	Unidirectional, determines addressable memory	Width (2^n addressable locations)
Control Bus	Control signal transmission	Read/write, interrupt, clock signals	Signal integrity, timing
System Bus	Connect CPU to memory	High-speed, connects major components	Bandwidth, latency
I/O Bus	Connect I/O devices	Various standards, slower	Standard compatibility